1. Field of the Invention
The invention relates to a programmable serial multiplier performing the multiplication of a multiplicand by a fixed constant which includes:
an addition cell formed by
a 1 bit full adder, PA1 a flip-flop which retards the carry in order to insert it into an input of the same adder, PA1 and a retard element operating on the result from the adder
It also relates to a computational processor performing a linear transform of data employing such a multiplier.
2. Description of the Related Art
Numerous embodiments of serial multipliers exist which are well suited to the processing of signals the regularity of the data streams of which makes it possible to exploit the pipelining possibilities of these serial multipliers. One particular class of these multipliers produces the product of a variable and a constant, then referred to as the coefficient. Applications thereof are found in filters, Fourier transforms, cosine transforms, etc. Advantage can be drawn from the fact that the constant is known when designing the circuit. It is then no longer necessary to provide data paths to route the coefficients. Such a multiplier is programmed by branching the corresponding inputs of the multiplier to 1 or to 0. It is easy to design but does not push to the limit the optimizations which are possible depending on the value of the coefficients. The optimization can be pushed much further: one example thereof is described in the patent "Method and digital circuit for fixed coefficient serial multiplication" GB 2,179,770 A.
This document proposes a serial multiplier which carries out multiplications of a multiplicand by a constant which is a fractional number. This constant is programmed by retarding the result obtained as output from the adder of the multiplier before inserting this result as input to this same adder in order to add it to the subsequent term. The result of a multiplication is therefore obtained after a computation time which depends on the fixed constant employed. This multiplier is not however designed to treat the cases of arbitrary constants. The structure of such a multiplier is therefore very dependent on the coefficients employed and this may pose difficulties whilst designing a circuit operating with multiple constants which it may be led to rapidly change at least cost.
In fact, modern methods of designing circuits and, in particular, integrated circuits, call upon computer aided design CAD techniques. A basic cell (for example a multiplier) is available in a library and, during design, it must be adapted to the operations which are to be carried out. It is therefore desirable that this basic cell is the most universal possible and may be adapted without difficulty to a vast field of possibilities. In particular, in the case of a multiplication by a constant, it is desirable that the type of constant does not call into question the fundamental structure of the multiplier. This should be solved by minimal attachments, readily and rapidly produced by the designer. In an integrated circuit context, the structure of the multiplier and hence the plan of the masks is an aspect which takes on great importance. A basic plan must be designed which is very close to the final structure and which is the least dependent possible on the coefficients to be inserted. Moreover, when it is desired to employ several serial multipliers of this type in a computational processor, it is necessary to try to minimize to the extent possible the specific operations for assemblage of cells. Stacks of serial multipliers, designed to order, are sometimes difficult to produce. This difficulty in readily designing stacks of several multipliers is coupled with another disadvantage relating to the speed of the processing carried out. In fact, with serial multipliers designed to order, each one has its own speed related to the coefficient processed, which does not make it possible to define common specifications and militates against the perfecting of the stack. CAD techniques find themselves affected thereby.